The present invention relates to the field of memory devices. More particularly, the invention relates to a method and arrangement for cascode barrel reading of data from a core memory of a memory device.
The overall array architecture for a typical integrated circuit containing a memory includes a core memory, herein referred to as a core, and input/output circuitry, herein referred to as the periphery. The core generally contains a plurality of core cells (i.e. individual memory elements) that are arranged in an array of rows and columns. The core cells contain at least one bit of data and are accessed through the periphery to external elements, such as a microprocessor, which require the data. The periphery includes the circuitry controlling the access of the core cells.
One arrangement by which data from the core may be accessed is by use of a plurality of cascodes and a plurality of sense amplifiers, herein referred to as samplers. In general, the cascodes determine the current or voltage from a core cell and the samplers sense the current or voltage from the cascode. When data from a core cell is requested, the cascode is accessed and outputs a result along a test bit line to the sampler. The output of the cascode is dependent on the state of the core cell. The sampler detects the difference between the test bit line containing the output of the cascode and a reference bit line containing the output of a reference cell. The sampler then compares the two bit lines and determines whether the core cell is programmed.
In general, when the core is accessed, the microprocessor or other external element requires a sizeable amount of data stored in consecutive core cells. This leads to a problem with the above arrangement. Because the delay through the cascode or time to obtain a valid output through the cascode, is large compared to the time to obtain a valid output from the sampler, the total amount of time for a set of data from consecutive core cells to be accessed is very large. Thus, especially with the huge increase in the speed of microprocessors (and other external elements), an increase in the access/readout speed of data from a set of consecutive core cells is beneficial.
In view of the above, a method and arrangement for cascode barrel reading of data from a core memory of a memory device is provided.
A first aspect of the invention is directed to a method for cascode barrel reading of data from a core memory of a memory device. The method comprises consecutively accessing a set of consecutive core cells contained in the plurality of core cells via a plurality of cascodes. Each cascode is connected with a subset of the set of consecutive core cells. An output of a set of the plurality of cascodes is sensed via at least one sampler and each sampler is connected with at least two cascodes. The core cells contained in the set of consecutive core cells are consecutively accessed and each cascode looks ahead such that after one of the pair of core cells in one cascode is accessed and the output of the one cascode is sensed by a corresponding sampler, the other of the pair of core cells in the one cascode is accessed during a time period in which the three core cells having addresses between the pair of core cells are consecutively accessed and sensed by the corresponding sampler.
The following figures and detailed description of the preferred embodiments will more clearly demonstrate these and other objects and advantages of the invention.